The present invention relates, in general, to the field of integrated circuit memory devices and those devices incorporating embedded memory. More particularly, the present invention relates to a data inversion register technique for integrated circuit memory testing which results in a maximization of the probability of identifying device failures during testing.
With today's standard dynamic random access memory (DRAM) devices, input/output (I/O) widths are becoming ever larger with 32 bit widths and wider being relatively common. In comparison, embedded DRAM circuits may contain even wider I/O widths including those having 256 data in (Din) and 256 data out (Dout) widths and wider.
Manufacturing testing of these wide I/O DRAM circuits is particularly challenging. Data compression test modes have been used to meet this challenge but these techniques lack the pattern capability needed to exercise the full memory array and data path. Further, conventional data path circuits do not have the capability for writing data stripes from a single data input signal.